Developed in a magic night of 19 Aug, 2018 between 2am and 8am, the DarkRISCV softcore started as an proof of concept for the opensource RISC-V instruction set. 

The general concept was based in early 16-bit RISC processors (uDarkRISC) and composed by a simplified DSP-like 2-stage pipeline, where a instruction is fetch from a instruction memory in the first clock and then the instruction is decoded/executed in the second  clock, peaking IPC = 1 by 80% of time, while a new 3-stage version works the same way but splits the decode/execute in two clocks, peaking IPC = 1 by 70% of time!

The pipeline is overlapped without interlocks or forwards like a DSP, in a way that the DarkRISCV can reach the performance of one clock per instruction most of time, except by a taken branch, where one or two clock are lost in the pipeline flush. Of course, in order to perform read operations in BlockRAMs in a single clock, one wait-state on data read is required, with minimal impact.

As result, the code is very compact, with some  hundred lines of obfuscated but beautiful Verilog code. 

After years of exciting sleepless nights of work and the help of lots of colleagues, the DarkRISCV reached a very good quality result, in a way that the code compiled by the standard GCC for RV32I worked fine!

Nowadays, DarkRISCV support a lot of features, including caches, extrernal SDRAM memory and probably one of the last RISC-V cores with big-endian support! 

[github.com/darklife/darkriscv]

The DarkRISCV is now available online in the EDA Playground, in a way that is possible change the Verilog codes for Simulation, the SoC and the DarkRISCV, as well run the Icarus Verilog Simulation and see the results both in the Log console as well the waveforms in the EPWave! 

Access the EDA Playground site and, in order to get more fun, remember to check the option to run the EPWave after the simulation run, enable the browser support for pop-ups and good hacking!

[ https://www.edaplayground.com/x/yiR ]

Some old, but interesting, free research papers:

• TE811: Signal Codification Simulation and Techniques (UFPR)

• TE815: GNS3 Network Simulator Tutorial  (UFPR)

• TE823: Delta-Sigma Converter ASIC (UFPR)

The papers are available in the [Google Drive]

Darklife supported some projects across the 90's in the area of Graphic Interfaces, Operating System Design and Microcontroller Development Support. Althrough some projects are obsolete or even incomplete, they may be used nowadays as reference for new projects:

• XSTEP4 Toolkit for X11 with NeXTSTEP look and feel

• LiquidFire OS for DragonBall 68328 processors

• uDarkRISC Simple 16-bit RISC processor

• HC908RTOS for HC908 processors